(1) Field of the Invention
This invention relates to a data processing apparatus, which is referred to as a central processing unit (CPU), a microprocessor or the like.
(2) Description of the Related Art
Some conventional data processing apparatuses are constructed so that memory is exclusively used as the operand of operations by operational instructions. In such apparatuses, predetermined operations are executed on the basis of an instruction consisting of an operation code indicating the type of the operation, two operand addresses indicating the locations of data in the memory, for example, a source operand address and a destination operand address.
Some conventional data processing apparatuses are provided with a register called an accumulator and other registers also, the accumulator being implicitly used as an operand. In such apparatuses, operations are executed on the basis of an instruction consisting of a single register designation code indicating the register to operate besides the accumulator.
Other conventional data processing apparatuses are provided with general-purpose registers, any of which can be combined to be the operands and operations are executed on the basis of an instruction consisting of an operation code indicating the type of an operation and two register designation codes indicating the register to operate. However, according to the firstly-mentioned apparatuses using memory exclusively as the operand, the instruction word is rather long because it demands an operand field having bit-length to accommodate two operand addresses. As a result, programs written by the use of such apparatuses tend to be large-sized.
According to the secondly-mentioned apparatuses provided with an accumulator, the instruction word can be short because the instruction merely needs a register field which can accommodate a single register designation code whose bit-length is shorter than that of the operand address. However, operations are assigned mainly to the accumulator, so that frequent moves of data are required between the accumulator and either the other registers or the memory. Such an increase in the number of instructions to be written in programs may decrease the speed of process of the programs as well as increase the program sizes.
According to the last-mentioned apparatuses provided with general-purpose registers, the number of instructions to be written in programs can be fairly decreased because any combination of the registers can be the operands. The instruction word can be comparatively short because the bit-length of the register designation code to be used is shorter than that of an operand address.
Nevertheless, it is difficult for such apparatuses to be constructed so that the sizes of programs can be minimized both by various kinds of operations being executed and they are executed in short instruction word length because of the following problem:
When a data processing apparatus is provided with, for example, 8 general-purpose registers, the bit-length of the register designation code to specify a register is made 3 bits; the instruction requires a 6-bit register field. Thus, an 8-bit instruction word length is not practical because usable instructions in that case are at most 4 types while 16-bit instruction word length is actually demanded to get sufficient numbers of instructions types.